IEEE Trans Image Process - Memory-efficient architecture for hysteresis thresholding and object feature extraction.

Tópicos

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Resumo

Hysteresis thresholding is a method that offers enhanced object detection. Due to its recursive nature, it is time consuming and requires a lot of memory resources. This makes it avoided in streaming processors with limited memory. We propose two versions of a memory-efficient and fast architecture for hysteresis thresholding: a high-accuracy pixel-based architecture and a faster block-based one at the expense of some loss in the accuracy. Both designs couple thresholding with connected component analysis and feature extraction in a single pass over the image. Unlike queue-based techniques, the proposed scheme treats candidate pixels almost as foreground until objects complete; a decision is then made to keep or discard these pixels. This allows processing on the fly, thus avoiding additional passes for handling candidate pixels and extracting object features. Moreover, labels are reused so only one row of compact labels is buffered. Both architectures are implemented in MATLAB and VHDL. Simulation results on a set of real and synthetic images show that the execution speed can attain an average increase up to 24? for the pixel-based and 52? for the block-based when compared to state-of-the-art techniques. The memory requirements are also drastically reduced by about 99%.

Resumo Limpo

hysteresi threshold method offer enhanc object detect due recurs natur time consum requir lot memori resourc make avoid stream processor limit memori propos two version memoryeffici fast architectur hysteresi threshold highaccuraci pixelbas architectur faster blockbas one expens loss accuraci design coupl threshold connect compon analysi featur extract singl pass imag unlik queuebas techniqu propos scheme treat candid pixel almost foreground object complet decis made keep discard pixel allow process fli thus avoid addit pass handl candid pixel extract object featur moreov label reus one row compact label buffer architectur implement matlab vhdl simul result set real synthet imag show execut speed can attain averag increas pixelbas blockbas compar stateoftheart techniqu memori requir also drastic reduc

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